Registers and RAM: Crash Course Computer Science #6
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Date: 2022-04-04
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Comments and reviews: 10
David
Those are SR-Latch and D-Latch. D-latch is a gated SR Latch. (Unoptimized for illustration purposes) Most have edge detection in synchronous circuits which can be called flip flops, while asynchronous use latches. Asynchronous circuits are screaming fast, yet power hungry. Most computer circuits are synchronous. ASICs tend to be the ones that are asynchronous but can be either or. A lot of SRAM is build around gate based memory which is costly in terms of area due to gates not wires. These gates need metal layers (wires) to interconnect, so what they do is use lower levels to increase density. Then connect them into cells which reduces wires that would waste area or density. So they use mid to upper layers for the wires of the cells. Better known as locality. SRAM is fast but expensive and power hungry. Slower DRAM uses more capacitor like mediums sometimes with a single transistor for driving versus whole gates which use multiple transistors. This allows an increase in density but lowers performance and possibly power. However power tends to increase with bit density, but increasing density may also lower power or normalize it out. One thing about wires is they tend to form low pass filters, which creates delays or limits performance. Architecture generally handles this which also tends to decide how the matrix is arranged. These factors also predict the tradeoff of wires to gates in said matrix.
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Those are SR-Latch and D-Latch. D-latch is a gated SR Latch. (Unoptimized for illustration purposes) Most have edge detection in synchronous circuits which can be called flip flops, while asynchronous use latches. Asynchronous circuits are screaming fast, yet power hungry. Most computer circuits are synchronous. ASICs tend to be the ones that are asynchronous but can be either or. A lot of SRAM is build around gate based memory which is costly in terms of area due to gates not wires. These gates need metal layers (wires) to interconnect, so what they do is use lower levels to increase density. Then connect them into cells which reduces wires that would waste area or density. So they use mid to upper layers for the wires of the cells. Better known as locality. SRAM is fast but expensive and power hungry. Slower DRAM uses more capacitor like mediums sometimes with a single transistor for driving versus whole gates which use multiple transistors. This allows an increase in density but lowers performance and possibly power. However power tends to increase with bit density, but increasing density may also lower power or normalize it out. One thing about wires is they tend to form low pass filters, which creates delays or limits performance. Architecture generally handles this which also tends to decide how the matrix is arranged. These factors also predict the tradeoff of wires to gates in said matrix.
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Joe
So question: How did the computer 'save' the bit at a low level before silicon wafers? Didn't it require electricity to run through the circuit? Wouldn't that mean it wouldn't have persistent memory since the electricity would turn off once you unplugged the computer? Or does the saved bit continue around the circuit without power?
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So question: How did the computer 'save' the bit at a low level before silicon wafers? Didn't it require electricity to run through the circuit? Wouldn't that mean it wouldn't have persistent memory since the electricity would turn off once you unplugged the computer? Or does the saved bit continue around the circuit without power?
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Yigit
When building the 256-Bit Memory, wouldn-t we be able to connect the grid so that each row connects to Write Enable and each column line connects to Data In/Out for that line of latches? (Assuming we didn-t need the Read Enable yet, so this would be for a very simple breadboard computer memory)
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When building the 256-Bit Memory, wouldn-t we be able to connect the grid so that each row connects to Write Enable and each column line connects to Data In/Out for that line of latches? (Assuming we didn-t need the Read Enable yet, so this would be for a very simple breadboard computer memory)
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Tristan
For me the multiplexer doesn-t seem to cover all possible 256-bit numbers. For example, if column 1 is required for one bit, and row 3 for another bit, then automatically the bit located at row 3 column 1 will also activate, even if I don-t want to. How does this work?
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For me the multiplexer doesn-t seem to cover all possible 256-bit numbers. For example, if column 1 is required for one bit, and row 3 for another bit, then automatically the bit located at row 3 column 1 will also activate, even if I don-t want to. How does this work?
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Khaled
I've struggled so much with my software for embedded systems course because these basic concepts were unclear to me. Few minutes into the video and a huge bulb lit up in my brain and I had this AHHAAAA moment! Thank you
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I've struggled so much with my software for embedded systems course because these basic concepts were unclear to me. Few minutes into the video and a huge bulb lit up in my brain and I had this AHHAAAA moment! Thank you
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sophy
Why use 256 bit memory to store just one bit data and how can a register of 8 256 bit memory store 256 bytes at 256 different location if each of them can store only one bit in one latch at a time
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Why use 256 bit memory to store just one bit data and how can a register of 8 256 bit memory store 256 bytes at 256 different location if each of them can store only one bit in one latch at a time
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Tyler
At the very end, she said, -Thanks for the random access memories-. Lol That is hilarious. Thank you for your way of educating about Computer Science; it's well received and appreciated.
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At the very end, she said, -Thanks for the random access memories-. Lol That is hilarious. Thank you for your way of educating about Computer Science; it's well received and appreciated.
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Nirav
Dear Carrie Anne,
thanks you very much for the whole series! Could you please suggest me literatures/ reference material for this episode?
Thanks and best regards
Nirav
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Dear Carrie Anne,
thanks you very much for the whole series! Could you please suggest me literatures/ reference material for this episode?
Thanks and best regards
Nirav
reply
Good
Brilliant! I am learning more from 1or 2 of these 10 min videos, than I learnt in allmost months while I was in engineering college. it's mind blowing when I think about it!
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Brilliant! I am learning more from 1or 2 of these 10 min videos, than I learnt in allmost months while I was in engineering college. it's mind blowing when I think about it!
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Romeo
The layers of abstraction gets really complex. I applaud the geniuses that have contributed to the development of computer data storage over the many years.
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The layers of abstraction gets really complex. I applaud the geniuses that have contributed to the development of computer data storage over the many years.
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