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AMD 3D V-Cache for Ryzen CPUs is Impressive: Up to 192MB L3 Cache

AMD 3D V-Cache for Ryzen CPUs is Impressive: Up to 192MB L3 Cache

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Rating: 4.0; Vote: 1
AMD s secret announcement is now out, and it s about AMD 3D V-Cache for Ryzen CPUs. This video details 3D V-Cache and talks further details about FidelityFX Super Resolution on NVIDIA. AMD s 3D V-Cache for Ryzen CPUs uses through-silicon vias and a hybrid bonding approach to connect 6x6mm S-RAM L3 cache to the top of the AMD CCXs (Core Complexes), but die sanding allows AMD to achieve a similar or the same package height and physical sizing. This could be a potential game changer for AMD as it works to iterate further on its existing multi-chip architecture, especially as Intel pushes hard to compete with its own Foveros and 3D packaging technology. Additionally in this video, we give more airtime to FidelityFX Super Resolution (FSR), following subsequent information from AMD during its broadcast. The earlier prebriefing didn t give us details on the GTX 1060 running FSR, and seeing that really tipped the scales in favor of AMD FSR -- at least socially -- as minimally a stopgap for those stuck on old GPUs with limited supply.
Date: 2021-06-01

Comments and reviews: 10


Steve, you made the point AMD can work with TSMC and leverage that relationship compared to Intel who have to do it in house. Frankly on the basis of a 2 vs 1 fist fight it is a valid argument however as a comparison of business scale AMD & TSMC vs Intel on the basis of research capability I think you got that totally out of balance. That is not to say Intel hasn't been asleep at the wheel on CPUs in recent years but even the most biased reports recognise the Intel giant is waking up. So far no comment by any CES presenter on how they are fixing supply issues for gamers or industry.
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Structural silicon -- basically AMD have got two slabs of undeveloped real estate positioned either side of the new die-on-die cache to make things level physically for contacting the integrated heat spreader. I can't see a technical problem with them making a V2.0 cache chip which is the full width of the underlying die but with twice or even three times this expanded cache. The result would by Ryzens with, say, 768MB of L3 cache and Threadrippers with a couple of GB of L3 cache. The price would be up there in lights though.
Interesting times.

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I wonder what will be the cost implications of this. On the one hand, they can increase yields by orders of magnitude, but that's not as important today. On the other hand, it's still a 45% larger die for a 15% increase in gaming performance. And perfectly stacking two dies with microscopic copper bumps is no easy feat.
I can see this making sense if they can offset some of the costs by reducing the process steps per die, especially that of the SRAM die. But I'm skeptical of that. Zen 4 might end up being pricey.

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Nvidia have AMD FSR with there lack of backward compatibility, even if it's no where near as good as DLSS 2 if it just looks better than non native resolution and helps older cards it's a big PR win.
Suspect if it's on PS5/Xbox it may get good support in the next few years.
DLSS is amazing but the only cards that have it have less need than the older ones.

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Is this really going to be L3 cache or actually L4? If it is L3 then does that mean there's no L3 cache on the CCX?
L4 cache has been tried on Intel's Crystal Well chips a few years ago and performed very well. those were 128MB.
Down the road, I see that this could be a real bonus for AMD's APUs, mitigating the bandwidth constraints of the RAM.

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So 96MB cache per core complex. Assuming the core complex on zen 4 still the same at 8 cores and rumor has it that zen 4 epyc will have 12 compute dies of 8 cores each for total 96 cores. So .... the cache could be .... 12 ccx X 96MB = 1,152 MB or 1.1GB cache!!! in comparison the latest Epyc in the market has 256MB cache for 64 cores.
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Considering that FSR is hardware-agnostic, a crucial difference between it and DLSS is that it doesn't need to be specifically supported by display drivers. If/when Nvidia decides to drop DLSS, it'll stop being supported on new hardware, whereas games releasing with an implementation of FSR will retain the functionality forever.
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I don't get the caginess when it comes to FSR, it's something that many old and new gpus may benefit from. If it only manages to work good on like 5 games and dies after two years it's still a win. It's not like it was a feature locked to and sold as part of a gpu architecture like dlss. Anyhow, great videos as always!
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I would be interested to get some kind of deep dive on the thermal implications and trade-offs of all of these silicon stacking solutions.
I also don't understand why they're using silicon as structural components when its thermal conductivity is so poor. Does that have to do with the thermal expansion characteristics?

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I had a thought about 3D stacked cache a few years ago back when HBM was a little more relevant in the regular consumer market. Half dismissed it out of thermal concerns. Crazy to think they actually managed it. Amazing.
Now I wonder if it s possible to do with cores too. Or some novel cooling solution.

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